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KM62V256D, KM62U256D Family
Document Title
32Kx8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0 1.0
History
Initial draft Finalize - Add 70ns part in KM62U256D Family - Show ICC read only, and increased value ICC = 2mA ICC Read = 5mA - Seperate ICC1 read and write ICC1 = 5mAICC1 Read = 5mA, ICC1 Write = 10mA - Improved standby current(ISB1) Commercial part : 10A5A Extended and Industrial part : 20A5A - Improved VIL(Min.) : 0.4V0.6V - Improved power dissipation : 0.7W1W
Draft Data
April 1, 1997 November 12, 1997
Remark
Preliminary Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO, LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0 November 1997
KM62V256D, KM62U256D Family
32Kx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
* Process Technology : TFT * Organization : 32Kx8 * Power Supply Voltage KM62V256D family : 2.7~3.3V KM62U256D family : 3.0~3.6V * Low Data Retention Voltage : 2V(Min) * Three state output and TTL Compatible * Package Type : 28-SOP-450 28-TSOP1-0813.4F/R
CMOS SRAM
GENERAL DESCRIPTION
The KM62V256D and KM62U256D families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature range and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Product Family KM62V256DL-L KM62U256DL-L KM62V256DLE-L KM62U256DLE-L KM62V256DLI-L KM62U256DLI-L Industrial(-40~85C) Extended(-25~85C) Operating Temperature VCC Range Speed (ns) 701)/100 701)/85/100 701)/100 70 /85/100 701)/100 701)/85/100
1)
Power Dissipation Standby (ISB1, Max) Operating (Icc2) PKG Type
Commercial(0~70C)
3.0V ~3.6V 2.7V ~ 3.3V 3.0V ~3.6V 2.7V ~ 3.3V 3.0V ~3.6V 2.7V ~ 3.3V
5A
35mA
28-SOP2) 28-TSOP1-F/R
1. The parameter is measured with 30pF test load. 2. KM62V256D Family support SOP package without 100ns speed bin.
PIN DESCRIPTION
OE A11 A9 A8 VCC A13 WE WE VCC A13 A14 A12 A8 A7 A6 A9 A5 A4 A11 A3 OE A3 A4 CS A5 A6 I/O8 A7 A12 I/O7 A14 I/O6 VCC WE I/O5 A13 A8 I/O4 A9 A11 A10 OE
14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24
FUNCTIONAL BLOCK DIAGRAM
A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2
Clk gen.
A13 A8 A12 A14 A4 A5 A6 A7
Precharge circuit.
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22
28-TSOP Type1 - Forward
23 22 21 20 19 18 17 16 15
Row select
Memory array 256 rows 128x8 columns
28-SOP
21 20 19 18 17 16 15
28-TSOP Type1 - Reverse
21 22 23 24 25 26 27 28
A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10 CS
I/O1 I/O8
Data cont
I/O Circuit Column select
Data cont
A10 A3
A0
A1 A2 A9
A11
Pin Name
CS OE WE A0~A14
Function
Chip Select Input Output Enable Input Write Enable Input Address Inputs
Pin Name
I/O1~I/O8 Vcc Vss NC
Function
WE
Control logic
Data Inputs/Outputs
OE
Power Ground No connect
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2
Revision 1.0 November 1997
KM62V256D, KM62U256D Family
PRODUCT LIST
Commercial Temperature Products (0~70C) Part Name
KM62V256DLG-7L KM62V256DLTG-7L KM62V256DLRG-7L
CMOS SRAM
Industrial Temperature Products (-40~85C) Part Name
KM62V256DLGI-7L KM62V256DLTGI-7L
Extended Temperature Products (-25~85C) Part Name
KM62V256DLGE-7L KM62V256DLTGE-7L
Function
28-SOP, 70ns, 3.3V 28-TSOP F, 70ns, 3.3V
Function
28-SOP, 70ns, 3.3V 28-TSOP F, 70ns, 3.3V
Function
28-SOP, 70ns, 3.3V 28-TSOP F, 70ns, 3.3V 28-TSOP R, 70ns, 3.3V
KM62V256DLTG-10L 28-TSOP F, 100ns, 3.3V KM62V256DLTGE-10L 28-TSOP F, 100ns, 3.3V KM62V256DLTGI-10L 28-TSOP F, 100ns, 3.3V 28-TSOP R, 70ns, 3.3V KM62V256DLRGE-7L 28-TSOP R, 70ns, 3.3V KM62V256DLRGI-7L KM62V256DLRG-10L 28-TSOP R, 100ns, 3.3V KM62V256DLRGE-10L 28-TSOP R, 100ns, 3.3V KM62V256DLRGI-10L 28-TSOP R, 100ns, 3.3V KM62U256DLG-7L KM62U256DLG-8L KM62U256DLG-10L KM62U256DLTG-7L KM62U256DLTG-8L 28-SOP, 70ns, 3.0V 28-SOP, 85ns, 3.0V 28-SOP, 100ns, 3.0V 28-TSOP F, 70ns, 3.0V 28-TSOP F, 85ns, 3.0V KM62U256DLGE-7L KM62U256DLGE-8L KM62U256DLGE-10L KM62U256DLTGE-7L KM62U256DLTGE-8L KM62U256DLRGE-7L 28-SOP, 70ns, 3.0V 28-SOP, 85ns, 3.0V 28-SOP, 100ns, 3.0V 28-TSOP F, 70ns, 3.0V 28-TSOP F, 85ns, 3.0V 28-TSOP R, 70ns, 3.0V 28-TSOP R, 85ns, 3.0V KM62U256DLGI-7L KM62U256DLGI-8L KM62U256DLGI-10L KM62U256DLTGI-7L KM62U256DLTGI-8L KM62U256DLRGI-7L KM62U256DLRGI-8L 28-SOP, 70ns, 3.0V 28-SOP, 85ns, 3.0V 28-SOP, 100ns, 3.0V 28-TSOP F, 70ns, 3.0V 28-TSOP F, 85ns, 3.0V 28-TSOP R, 70ns, 3.0V 28-TSOP R, 85ns, 3.0V
KM62U256DLTG-10L 28-TSOP F, 100ns, 3.0V KM62U256DLTGE-10L 28-TSOP F, 100ns, 3.0V KM62U256DLTGI-10L 28-TSOP F, 100ns, 3.0V KM62U256DLRG-7L 28-TSOP R, 70ns, 3.0V KM62U256DLRG-8L 28-TSOP R, 85ns, 3.0V KM62U256DLRGE-8L
KM62U256DLRG-10L 28-TSOP R, 100ns, 3.0V KM62U256DLRGE-10L 28-TSOP R, 100ns, 3.0V KM62U256DLRGI-10L 28-TSOP R, 100ns, 3.0V
FUNCTIONAL DESCRIPTION
CS H L L L OE X
1)
WE X
1)
I/O High-Z High-Z Dout Din
Mode Deselected Output Disabled Read Write
Power Standby Active Active Active
H L X
1)
H H L
1. X means dont care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.5 to VCC+0.5 -0.5 to 4.6 1.0 -65 to 150 0 to 70 -25 to 85 -40 to 85 Soldering temperature and time TSOLDER 260C, 10sec (Lead Only) Unit V V W C C C C Remark KM62V256DL, KM62U256DL KM62V256DLE, KM62U256DLE KM62V256DLI, KM62U256DLI -
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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Revision 1.0 November 1997
KM62V256D, KM62U256D Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Product KM62V256D Family KM62U256D Family ALL KM62V256D, KM62U256D Family KM62V256D, KM62U256D Family Min 3.0 2.7 0 2.2 -0.33) Typ 3.3 3.0 0 -
CMOS SRAM
Max 3.6 3.3 0 Vcc+0.3 0.6 V V V Unit V
Note: 1. Commercial Product : TA=0 to 70C, otherwise specified Industrial Product : TA=-40 to 85C, otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width30ns 3. Undershoot : -3.0V in case of pulse width30ns 4. Overshoot and undershoot are sampled, not 100% tested
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Average operating current Symbol ILI ILO ICC ICC1 ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current (CMOS) VOL VOH ISB ISB1 VIN=Vss to Vcc CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc IIO=0mA, CS=VIL, VIN=VIH or VIL, Read Cycle time=1s, 100% duty, IIO=0mA CS0.2V, VIN0.2V, VINVcc -0.2V Read Write 2.4 Test Conditions Min -1 -1 Typ 2 1.5 6 23 0.1 Max 1 1 5 5 10 35 0.4 0.3 5 mA V V mA A Unit A A mA mA
Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL IOL=2.1mA IOH=-1.0mA CS=VIH, Other inputs=VIH or VIL CSVcc-0.2V, Other inputs=0~Vcc
4
Revision 1.0 November 1997
KM62V256D, KM62U256D Family
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL1)=30pF+1TTL
1. Refer to AC CHARACTERISTICS
CMOS SRAM
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS (KM62V256D Family:Vcc=3.0~3.6V, KM62U256D Family:Vcc=2.7~3.3V
Commercial product :TA=0 to 70C, Extended product :TA=-25 to 85C, Industrial product :TA=-40 to 85C)
Speed Bins Parameter List Symbol 701)ns Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z
1. The parameter is measured with 30pF test load
85ns Min 85 10 5 0 0 10 85 70 0 70 60 0 0 35 0 10 Max 85 85 40 30 30 25 Min 100 10 5 0 0 15 100 80 0 80 70 0 0 40 0 10
100ns Max 100 100 50 35 35 35 -
Units
Max 70 70 35 30 30 25 -
tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW
70 10 5 0 0 5 70 60 0 60 50 0 0 30 0 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CSVcc-0.2V Vcc=3.0V, CSVcc-0.2V See data retention waveform Min 2.0 0 5 Typ Max 3.6 5 Unit V A ms
5
Revision 1.0 November 1997
KM62V256D, KM62U256D Family
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC Address tOH Data Out Previous Data Valid tAA
CMOS SRAM
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO CS tOE OE tOLZ tLZ Data Valid tOHZ tHZ tOH
Data out
NOTES (READ CYCLE)
High-Z
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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Revision 1.0 November 1997
KM62V256D, KM62U256D Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS tAW tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4)
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2) (CS
Controlled)
tWC Address tAS(3) CS tAW tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC 3.0/2.7V tSDR Data Retention Mode tRDR
2.2V VDR CSVCC - 0.2V CS GND
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Revision 1.0 November 1997
KM62V256D, KM62U256D Family
PACKAGE DIMENSIONS
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)
CMOS SRAM
Units :millimeter(inch)
0~8 #28 #15
11.810.30 0.4650.012
8.380.20 0.3300.008
#1 18.69 MAX 0.736 18.290.20 0.7200.008
#14 2.590.20 0.1020.008 3.00 0.118 MAX
11.43 0.450
+0.10 -0.05 0.006 +0.004 -0.002
0.15
1.020.20 0.0400.008
0.10 MAX 0.004 MAX ( 0.89 ) 0.035 0.410.10 0.0160.004 1.27 0.050
0.05 MIN 0.002
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Revision 1.0 November 1997
KM62V256D, KM62U256D Family
PACKAGE DIMENSIONS
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F)
13.400.20 0.5280.008 #28
CMOS SRAM
Units :millimeter(inch)
0.10 MAX 0.004 MAX
+0.10 -0.05 +0.004 0.008-0.002
0.20
#1
( 8.40 0.331 MAX 8.00 0.315
0.425 ) 0.017
0.55 0.0217
#14 0.25 0.010 TYP 11.800.10 0.4650.004
#15
+0.10 -0.05 0.006+0.004 -0.002
0.15
1.000.10 0.0390.004 1.20 0.047 MAX
0.05 0.002 MIN
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R)
+0.10 -0.05 +0.004 0.008-0.002
0.20
13.400.20 0.5280.008 #15 ( 8.40 0.331 MAX 8.00 0.315 0.425 ) 0.017
#14
0.55 0.0217
#1
#28 1.000.10 0.0390.004 1.20 0.047 MAX 0.05 0.002 MIN
0.25 0.010 TYP
11.800.10 0.4650.004
+0.10 -0.05 0.006+0.004 -0.002
0.15
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
9
0.10 MAX 0.004 MAX
Revision 1.0 November 1997

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